Saeid Rajabi

ECE Ph.D. Candidate at University of Delaware

Hi, I'm Saeid, a Ph.D. candidate at the University of Delaware, co-advised by Dr. Chengmo Yang and Dr. Satwik Patnaik.

My research focuses on Large Language Models (LLMs) and Artificial Intelligence (AI) for hardware design, verification, and chip design, integrating LLMs, deep learning, and reinforcement learning into modern Electronic Design Automation (EDA) workflows to make them more automated, secure, and trustworthy.

Always happy to discuss research; feel free to reach out at srajabi [at] udel [dot] edu.

News

May 6, 2026🥇 Received the best poster award in the ECE department for STELLAR.
Apr 1, 2026🏆 Awarded Young Fellow at DAC 2026.
Feb. 2026Our paper STELLAR on structure-guided LLM assertion retrieval and generation for formal verification is accepted at DAC 2026.
Feb. 2025Our paper on Key-Recovery Attack on Enhanced PSLL Techniques is accepted at IEEE Embedded Systems Letters.

Publications

DAC'26

STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verification

A structure-guided retrieval and generation methodology that grounds LLMs in expert-written verification codebases to produce SystemVerilog Assertions at industrial complexity.

arXiv BibTeX

IEEE ESL'25

Key-Recovery Attack on Enhanced PSLL Techniques

A framework that breaks advanced provably-secure logic-locking techniques by combining structural analysis with IC testing to fully recover secret keys.

DOI BibTeX

Teaching

Spring 2026GTA, IoT & Embedded Systems Security (CPEG 475/675) (Prof. Patnaik) and Embedded Systems HW/SW Co-Design (CPEG 422/622) (Prof. Yang), University of Delaware.
Fall 2025GTA, Microprocessors (CPEG 222) (Prof. Martin), University of Delaware.
2021 – 2023TA, Microprocessors and Micro-controllers (Prof. Darmani), K. N. Toosi University of Technology (4 semesters).

Professional Activities

Reviewer (sub): DAC, ICCAD, HOST, IEEE TCAD, IEEE TVLSI, ACM TODAES.