Saeid Rajabi
ECE Ph.D. Candidate at University of Delaware
Hi, I'm Saeid, a Ph.D. candidate at the University of Delaware, co-advised by Dr. Chengmo Yang and Dr. Satwik Patnaik.
My research focuses on Large Language Models (LLMs) and Artificial Intelligence (AI) for hardware design, verification, and chip design, integrating LLMs, deep learning, and reinforcement learning into modern Electronic Design Automation (EDA) workflows to make them more automated, secure, and trustworthy.
Always happy to discuss research; feel free to reach out at srajabi [at] udel [dot] edu.
STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verification
A structure-guided retrieval and generation methodology that grounds LLMs in expert-written verification codebases to produce SystemVerilog Assertions at industrial complexity.
AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting
The first benchmark that evaluates LLMs on porting analog circuits across technology nodes, with tasks tiered by specification difficulty, studying reasoning effort, simulation feedback, and refusal of infeasible specifications.
Key-Recovery Attack on Enhanced PSLL Techniques
A framework that breaks advanced provably-secure logic-locking techniques by combining structural analysis with IC testing to fully recover secret keys.
Reviewer (sub): DAC, ICCAD, HOST, IEEE TCAD, IEEE TVLSI, ACM TODAES.