Saeid Rajabi
Ph.D. Candidate, Electrical & Computer Engineering — University of Delaware
Education
Aug 2023 – Present
Ph.D. Candidate, Electrical and Computer Engineering
- GPA: 3.92/4.0
- Co-advisors: Dr. Chengmo Yang, Dr. Satwik Patnaik
- Research Area: Large Language Models and AI/ML for Hardware Design, Verification, and EDA; Hardware Security and Secure EDA
- Selected coursework: Machine Learning (A), Embedded Systems Co-Design (A), VLSI Systems (A), Applied Cryptography (A), Parallel Computer Architecture (A-)
Sep 2018 – Feb 2023
B.Sc. in Electrical & Electronics Engineering
- GPA: 16.41/20
- CS coursework: Data Structures, Algorithms, Advanced Programming
Research Experience
Sep 2023 – Present
Graduate Research Assistant
- Research at the intersection of AI and hardware/chip design, integrating LLMs, deep learning, and reinforcement learning into chip design security and verification.
- Developed frameworks for automating power side-channel analysis and logic obfuscation, improving design robustness and reducing manual engineering effort.
- AI-guided secure Electronic Design Automation (EDA) flows for next-generation trustworthy hardware systems.
May 2022 – Feb 2023
Undergraduate Researcher (Thesis Project)
- Title: Anomaly Detection in Smart Grid Electricity Consumers.
- Built intelligent systems to identify fraudulent electricity usage such as unauthorized cryptocurrency mining.
- Designed a multi-layer detection pipeline combining statistical analysis, pattern recognition, and LSTM-based time-series prediction.
Mar 2020 – Dec 2020
Research Collaborator, Unified Communication System Project
- Contributed to deployment of a company-wide unified communication system.
- Integrated video conferencing, VoIP, and instant messaging platforms to streamline internal communication.
Teaching
Feb 2026 – Present
TA, University of Delaware
- IoT and Embedded Systems Security (CPEG 475/675) — Prof. Satwik Patnaik
- Embedded Systems HW/SW Co-Design (CPEG 422/622) — Prof. Chengmo Yang
- Two graduate/senior-level courses concurrently: delivering lectures, presenting lab demonstrations, designing homework assignments, office hours, grading.
Sep 2025 – Jan 2026
TA, University of Delaware
- Microprocessors (CPEG 222) — Prof. Richard Martin
- Sole graduate TA; coordinated undergraduate Supplemental Instructors; led recitations; office hours; grading; dispute resolution.
Sep 2021 – Feb 2023
TA, K. N. Toosi University of Technology
- Microprocessors and Micro-controllers — Prof. Yousef Darmani (4 semesters)
- Supported test administration, curriculum development, grading, and tutoring.
Service
- Reviewer: ISVLSI 2025; IEEE ESL.
- Sub-reviewer (under Dr. Satwik Patnaik): DAC 2024, 2026; ICCAD 2026; IEEE TCAD; IEEE TVLSI; ACM TODAES; IEEE Access.
- Sub-reviewer (under Dr. Chengmo Yang): ICCAD 2026; HOST 2025.
Technical Skills
- Programming Languages: Python, C, C++, Java, TCL, MATLAB, SQL, Assembly, Bash
- AI/ML: LLM Fine-Tuning and Alignment, Retrieval-Augmented Generation (RAG), Machine Learning, Deep Learning, Reinforcement Learning, Meta-Learning
- Hardware Design & Verification: RTL Design, Verilog, VHDL, Logic Locking, Functional Verification, Formal Verification, Power Side-Channel Analysis
- EDA & Development Tools: Cadence Genus, XCELIUM, Joules, JasperGold, LEC Verification, Innovus, Virtuoso, PSpice; Xilinx ISE, Proteus, ADS; Git/GitHub; Linux
- Computer Architecture & CAD: RTL-to-GDSII flow, Logic Synthesis, Timing Analysis, Formal Equivalence Checking, Physical Verification (LVS, DRC, ERC)
Selected Projects
- Neural Network Acceleration Using FPGA — HW/SW co-design system accelerating a quantized CNN for MNIST digit recognition; convolution layers on FPGA via AXI interfaces for higher throughput and energy efficiency.
- PSC-Aware ASIC Logic Synthesis — Iterative refinement to identify and fix sources of power side-channel leakage; integrated with Cadence tools for industry adaptation.
- Security-Aware Logic Synthesis with Reinforcement Learning — RL framework for security-aware hardware synthesis; improved robustness of logic-obfuscated circuits against ML-based reverse engineering.
- IoT Security Through Meta-Learning — Meta-learning pipeline adapting to new cyberattack patterns in IoT devices with limited training data; multi-class intrusion detection.
- Intrusion Detection System — ML models (Logistic Regression, SVM, Decision Tree, MLP) for network-traffic anomaly detection; binary and multi-class classification.
- Logic Locking from RTL to Physical Layout — Implementation of state-of-the-art logic locking schemes across the full design flow, from netlist to chip layout.
- Gate-Level Logic Locking & Structural Attacks — Anti-SAT, SARLock, and random key insertion to secure HW IP; structural attack strategies to benchmark resilience.
- IoT-based Smart Agricultural Framework — End-to-end system using Raspberry Pi 4, sensors, and wireless modules to monitor dissolved oxygen, turbidity, nitrite, ammonia, and pH; learning-based analysis tying environmental parameters to business outcomes.
- Edge Detection Using FPGA — Hardware accelerator for image edge detection using neural networks; comparison of MLP architectures and activation functions for accuracy/speed.